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datasheet AX8052F151 soc ultra - low power rf - microcontroller for the 400 - 470 mhz and 800 - 940 mhz bands revision 2
www.onsemi.com AX8052F151 2 table of contents 1. overview .................................................................................................................. 5 1.1. features .................................................................................................................... 5 1.2. applications ............................................................................................................... 6 2. b lock diagram .......................................................................................................... 7 3. pin function descriptions ......................................................................................... 8 3.1. alternate pin functions ................................................................................................ 9 3.2. pinout drawing .......................................................................................................... 10 4. specifications ......................................................................................................... 11 4.1. absolute maximum ratings ......................................................................................... 11 4.2. dc characteristics ..................................................................................................... 12 supplies .................................................................................................................... 12 logic ........................................................................................................................ 15 4.3. ac characteristics ...................................................................................................... 16 crystal oscillator (rf reference oscillator) ..................................................................... 16 rf frequency generation subsystem (synthesi zer) ........................................................ 17 transmitter ............................................................................................................... 19 receiver .................................................................................................................... 19 low frequency crystal oscilla tor .................................................................................. 21 internal low power oscillator ...................................................................................... 21 internal rc oscillator .................................................................................................. 21 microcontroller ........................................................................................................... 22 adc / comparator / temperature sensor ...................................................................... 23 5. circuit description .................................................................................................. 24 5.1. microcontroller .......................................................................................................... 25 memory architecture .................................................................................................. 25 memory map .............................................................................................................. 26 power management .................................................................................................... 27 clocking .................................................................................................................... 28
table of contents www.onsemi.com AX8052F151 3 reset and interrupts .................................................................................................. 29 debugging ................................................................................................................ 29 5.2. timer, output compare and input capture ................................................................... 30 5.3. uart ....................................................................................................................... 30 5.4. spi master/slave controller ........................................................................................ 30 5.5. adc, analog comparators and temperature sensor ....................................................... 31 5.6. dma contr oller .......................................................................................................... 32 5.7. aes engine ............................................................................................................... 32 5.8. crystal oscillator (rf reference oscillator) ..................................................................... 32 5.9. sysclk output .......................................................................................................... 33 5.10. power - on - reset (por) and reset_n input ............................................................... 33 5.11. ports ................................................................................................................... 34 6. transceiver ............................................................................................................ 35 6.1. rf frequency generation subsystem ........................................................................... 35 vco ......................................................................................................................... 35 vco auto - ranging ..................................................................................................... 35 loop filter and charge pump ....................................................................................... 36 registers ................................................................................................................... 36 6.2. rf input and output stage (antp/antn) ..................................................................... 37 lna .......................................................................................................................... 37 i/q mixer .................................................................................................................. 37 pa ............................................................................................................................ 37 6.3. analog if filter .......................................................................................................... 37 6.4. digital if channel filter and demodulator ..................................................................... 37 registers ................................................................................................................... 38 6.5. encoder .................................................................................................................... 38 6.6. framing and fifo ...................................................................................................... 39 hdlc mode ............................................................................................................... 40 raw mode ................................................................................................................ 40 raw mode with preamble match .................................................................................. 40
overview www.onsemi.com AX8052F151 4 802.15.4 (zigbee) dsss ............................................................................................. 40 6.7. rx agc and rssi ...................................................................................................... 41 6.8. modulator ................................................................................................................. 41 6.9. automatic frequency control (afc) .............................................................................. 42 6.10. pwrmode register ............................................................................................... 42 6.11. voltage regulator .................................................................................................. 44 7. application information ......................................................................................... 45 connecting to debug adapter ...................................................................................... 45 7.1. antenna interface circuitry ......................................................................................... 46 single - ended antenna interface ................................................................................... 46 8. qfn40 package information .................................................................................. 47 8.1. package outline qfn40 .............................................................................................. 47 8.2. qfn40 soldering profile .............................................................................................. 48 8.3. qfn40 recomm ended pad layout ................................................................................ 49 8.4. assembly process ...................................................................................................... 49 stencil design & solder paste application ...................................................................... 49 9. device versions ...................................................................................................... 51
overview www.onsemi.com AX8052F151 5 1. overview 1.1. features soc ultra - low power rf - microcontroller for wireless communication applications ? qfn40 package ? supply range 2.2v - 3.6v (1.8v mcu) ? - 40c to 85c ? ultra - low pow er consumption: o cpu active mode 150 a/mhz o sleep mode with 256 byte ram retention and wake - up timer running 900 n a o sleep mode 4 kbyte ram retention and wake - up timer running 1.9 a o sleep mode 8 kbyte ram retention and wake - up timer running 2.6 a o radio rx - mode in low power mode 17 ma o radio tx - mode 22 ma at 10 dbm output power o wake - on - radio mode 100 kbps, 1s duty cycle 6 a ? ax8052 features o ultra - low power mcu core compatible with industry standard 8052 instruction set o down to 500 na wake - up current o 1 cycle /instruction for many instructions o 64 kbyte in - system programmable flash o code protection lock o 8.25 kbyte sram o 3 - wire (1 dedicated, 2 shared) in - circuit debug interface o 3 16- bit timers with ? output capability o 2 16- bit wakeup timers o 2 input captures o 2 outp ut compares with pwm capability o 10- bit 500 ksample/s analog- to - digital converter o temperature sensor o 2 analog comparators o 2 uarts o 1 general purpose master/slave spi o 2 channel dma controller o multi - megabit/s aes encryption/decryption engine, supports aes - 128, aes- 192 and aes- 256 with true random number generator (trng) 1 o ultra - low power 10 khz/640 hz wakeup oscillator, with automatic calibration against a precise clock o internal 20 mhz rc oscillator, with automatic calibration against a precise clock for flexibl e system clocking o low frequency tuning fork crystal oscillator for accurate low power time keeping o brown - out and power - on - reset detection ? high - performance rf transceiver compatible to ax5051 o 400- 470 mhz and 800- 940 mhz srd bands o wide variety of shaped mo dulations supported (ask, psk, msk, fsk) o flexible shaping for the modulations o data rates from 1 to 350 kbps (fsk, msk) and 1 to 600 kbps ask, 10 to 600 kbps psk o fully integrated rf frequency synthesizer with ultra - fast settling time for low - power consumpt ion o rf carrier frequency and fsk deviation programmable in 1 hz steps 1 the aes engine and t he trng require software enabling and support.
overview www.onsemi.com AX8052F151 6 o variable channel filtering from 40 khz to 600 khz o 802.15.4 compatible o few external components o channel hopping up to 2000 hops/s o sensitivity down to ? 116 dbm at 1.2 kbps o up to +16 dbm at 433 mhz programmable transmitter power amplifier for long range operation o crystal oscillator with programmable transconductance and programmable internal tuning capacitors for low cost crystals o digital rssi o automatic frequency control (afc) o integrat ed rx/tx switching o differential antenna pins o support of synchronous and asynchronous communication systems 1.2. applications 400- 470 mhz and 800 - 940 mhz data transmission and reception in the short range devices (srd) band. ? suited for systems tar geting compliance to en 300 220 v2.3.1 and fcc cfr part 15 ? suited for systems targeting compliance with wireless m - bus standard en 13757 - 4:2005 ? 802.15.4 compatible ? telemetric applications, sensor readout ? toys ? wireless audio ? automatic meter reading ? wireles s networks ? access control ? remote keyless entry ? garage door openers ? home automation ? pointing devices and keyboards ? active rfid
block diagram www.onsemi.com AX8052F151 7 2. block diagram AX8052F151 antp antn if filter and agc pgas agc crystal oscillator typ. 16mhz f out rf frequency generation subsystem f xtal communication controller & radio interface controller lna divider adc digital if channel filter pa de- modulator encoder framing fifo modulator mixer clk16p clk16n rssi radio configuration vreg voltage regulator por 256 debug interface axsem 8052 system controller flash 64k aes crypto engine adc comparators spi master/slave uart 1 uart 0 input capture 1 input capture 0 output compare 1 output compare0 timer counter 2 timer counter 1 timer counter 0 gpio pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 reset_n gnd vdd_io 8k ram pc0 pc1 pc2 pc3 pc4 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 i/o multiplexer dbg_en irq req reset, clocks, power i-bus p-bus x-bus sfr-bus dma controller dma req sysc lk vdda temp sensor wakeup oscillator rc oscillator tuning fork crystal oscillator wakeup timer 2x figure 1 functional block diagram of the AX8052F151
pin function descriptions www.onsemi.com AX8052F151 8 3. pin function descriptions symbol pin(s) type description gnd 1 p ground gnd 2 p ground vdda 3 p power supply, must be supplied with regulated voltage vreg gnd 4 p ground antp 5 a antenna input/output ant n 6 a antenna input/output gnd 7 p ground vdda 8 p power supply, must be supplied with regulated voltage vreg tst1 9 i connected to gnd tst 10 i connected to gnd vdd_io 11 p unregulated power supply (battery input) sysclk 12 i/o/pu system clock outpu t pc4 13 i/o/pu general purpose io pc3 14 i/o/pu general purpose io pc2 15 i/o/pu general purpose io pc1 16 i/o/pu general purpose io pc0 17 i/o/pu general purpose io pb0 18 i/o/pu general purpose io pb1 19 i/o/pu general purpose io pb2 20 i/o/pu g eneral purpose io pb3 21 i/o/pu general purpose io pb4 22 i/o/pu general purpose io pb5 23 i/o/pu general purpose io pb6 24 i/o/pu general purpose io, dbg_data pb7 25 i/o/pu general purpose io, dbg_clk dbg_en 26 i /pd in - circuit debugger enable reset _n 27 i /pu optional reset pin if this pin is not used it must be connected to vdd_io gnd 28 p ground vdd_io 29 p unregulated power supply (battery input) pa0 30 i/o/a/pu general purpose io pa1 31 i/o/a/pu general purpose io pa2 32 i/o/a/pu general pur pose io pa3 33 i/o/a/pu general purpose io pa4 34 i/o/a/pu general purpose io pa5 35 i/o/a/pu general purpose io pa6 36 i/o/a/pu general purpose io pa7 37 i/o/a/pu general purpose io
pin function descriptions www.onsemi.com AX8052F151 9 symbol pin(s) type description vreg 38 p regulated output voltage vdda pins must be connected to t his supply voltage a 1f low esr capacitor to gnd must be connected to this pin clk16p 39 a crystal oscillator input/output (rf reference) clk16n 40 a crystal oscillator input/output (rf reference) gnd center pad p ground on center pad of qfn, must be c onnected a = analog signal i/o = digital input/output signal i = digital input signal n = not to be connected o = digital output signal p = power or ground pu = pull - up pd = pull - down all digital inputs are schmitt trigger inputs, digital in put and output levels are lvcmos/lvttl compatible. port a pins (pa0 - pa7) must not be driven above vdd_io, all other digital inputs are 5v tolerant. pull - ups are programmable for all gpio pins. 3.1. alternate pin functions gpio pins are shared with dedicated i nput/output signals of on - chip peripherals. the following table lists the available functions on each gpio pin. gpio alternate functions pa0 t0out ic1 adc0 pa1 t0clk oc1 adc1 pa2 oc0 u1rx adc2 compi00 pa3 t1out adc3 lpxtalp pa4 t1clk compo0 adc4 lp xtaln pa5 ic0 u1tx adc5 compi10 pa6 t2out adctrig adc6 compi01 pa7 t2clk compo1 adc7 compi11 pb0 u1tx ic1 extirq0 pb1 u1rx oc1 pb2 ic0 t2out pb3 oc0 t2clk extirq1 dswake pb4 u0tx t1clk pb5 u0rx t1out pb6 dbg_data pb7 dbg_clk pc0 ssel t0out extirq0 pc1 ssck t0clk compo1 pc2 smosi u0tx pc3 smiso u0rx compo0 pc4 compo1 adctrig extirq1
pin function descriptions www.onsemi.com AX8052F151 10 3.2. pinout drawing AX8052F151 qfn40 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 40 39 38 37 36 35 34 33 32 31 30 29 gnd vdda gnd gnd antp antn vdda gnd tst1 tst2 vdd_io sysclk extirq1/adctrig/compo1/pc4 compo0/u0rx/smiso/pc3 u0tx/smosi/pc2 compo1/t0clk/ssck/pc1 extirq0/t0out/ssel/pc0 extirq0/ic1/u1tx/pb0 oc1/u1rx/pb1 t2out/ic0/pb2 clk16n clk16p vreg pa7/adc7/t2clk/compo1/compi11 pa6/adc6/t2out/adctrig/compi01 pa5/adc5/ic0/u1tx/compi10 pa4/adc4/t1clk/compo0/lpxtaln pa3/adc3/t1out/lpxtalp pa2/adc2/oc0/u1rx/compi00 pa1/adc1/t0clk/oc1 pa0/adc0/t0out/ic1 vdd_io gnd reset_n dbg_en pb7/dbg_clk pb6/dbg_data pb5/u0rx/t1out pb4/u0tx/t1clk pb3/oc0/t2clk/extirq1/dswake figure 2 pinout drawing (top view)
specifications www.onsemi.com AX8052F151 11 4. specifications 4.1. absolute maximum rat ings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of t his specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol description condition min max unit vdd_io supply voltage - 0.5 5.5 v idd supply current 100 ma p tot total powe r consumption 800 mw p i absolute maximum input power at receiver input 15 dbm i i1 dc current into any pin except antp, antn - 10 10 ma i i2 dc current into pins antp, antn - 100 100 ma i o output current 40 ma v ia input voltage antp, antn pins - 0 .5 5.5 v input voltage digital pins - 0.5 5.5 v v es electrostatic handling hbm - 2000 2000 v t amb operating temperature - 40 85 c t stg storage temperature - 65 150 c t j junction temperature 150 c
specifications www.onsemi.com AX8052F151 12 4.2. dc characteristics supplies symbol description condition min typ max unit t amb operational ambient temperature - 40 27 85 c vdd_io i/o and voltage regulator supply voltage rx operation or tx operation up to 4 dbm output power 2.2 3.0 3.6 v tx operation up to 16 dbm output power 2.4 3.0 3.6 v transceiver switched off 1.8 3.0 3.6 v vdd io_r1 i/o voltage ramp for reset activation; note 1 ramp starts at vdd_io0.1v 0.1 v/ms vdd io_r2 i/o voltage ramp for reset activation; note 1 ramp starts at 0.1v specifications www.onsemi.com AX8052F151 13 tx varvdd variation of output power over voltage vdd_io>2.5v, note 2 +/ - 0.5 db tx vartemp variation of output power over temperature vdd_io>2.5v, note 2 +/ - 0.5 db i mcu microcontroller running power consumption all peripherals disabled 150 a/ mhz i vsup voltage supervisor run and standby mode 85 a i xtalosc crystal oscillator current (rf reference oscillator) 16 mhz 160 a i lfxtalosc low frequency crystal oscilla tor current 32 khz 700 na i rcosc internal oscillator current 20 mhz 210 a i lposc internal low power oscillator current 10 khz 650 na 640 hz 210 na i adc adc current 311 ksample/s, dma 5 mhz 1.1 ma i wor typical wake - on - radio duty cycle curr ent 1s, 100 kbps 6 a notes: 1. if vdd_io ramps cannot be guaranteed, an external reset circuit is recommended, see the ax8052 application note: power on reset. 2. the pa voltage is regulated to 2.5 v. for vdd_io levels in the range of 2.2 v to 2.5 v the output power drops by typically 1 dbm.
specifications www.onsemi.com AX8052F151 1 4 note on current consumption in tx mode to achieve best output power the matching network has to be optimized for the desired output power and frequency. as a rule of thumb a good matching network produces about 50 % efficiency with the AX8052F151 power amplifier although over 90% are theoretically possible. a typical matching network has between 1 db and 2 db loss (p loss ). the current consumption can be calculated as i tx [ma]= 1/pa efficiency *10^((p out [dbm]+p loss [db])/10)/2.5v+i offset i offset is about 12 ma for the vco at 400 - 470 mhz and 11 ma for 800 - 940 mhz. the following table shows calculated current consumptions versus output power for p loss = 1 db, pa efficiency = 0.5 and i o ffset = 11 ma at 868 mhz pout [dbm] i [ma] 0 13.0 1 13.2 2 13.6 3 14.0 4 14.5 5 15.1 6 16.0 7 17.0 8 18.3 9 20.0 10 22.0 11 24.6 12 27.96 13 32.1 14 37.3 15 43.8 the AX8052F151 power amplifier runs from the regulated vdd supply and not directly from the battery. this has the advantage that the current and output power do not vary much over supply voltage and temperature from 2.55 v to 3.6 v supply voltage. between 2.55 v and 2.2 v a drop of about 1 db in output power occurs.
specifications www.onsemi.com AX8052F151 15 logic symbol description condition min typ max unit digital inputs v t+ schmitt trigger low to high threshold point vdd_io = 3.3v 1.55 v v t - schmitt trigger high to low threshold point 1.25 v v il input voltage, low 0.8 v v ih input voltage, high 2.0 v v ipa input voltage range, port a - 0.5 vdd_io v v ipbc input voltage range, ports b, c - 0.5 5.5 v i l input leakage current - 10 10 a r pu programmable pull - up resistance 65 k ? digital outputs i oh p[abc]x output current, high v oh = 2.4v 8 ma i ol p[abc]x output current, low v ol = 0.4v 8 ma i proh sysclk output current, high v oh = 2.4v 8 ma i prol sysclk output current, low v ol = 0.4v 8 ma i oz tri - state output leakage current - 10 10 a
specifications www.onsemi.com AX8052F151 16 4.3. ac character istics crystal oscillator (rf reference oscillator) symbol description condition min typ max unit f xtal crystal frequency note 1, 3 15.5 16 25 mhz gm osc transconductance oscillator ax5051_xtaloscgm=0000 1 ms ax5051_xtaloscgm=0001 2 ax5051_xtal oscgm =0010 default 3 ax5051_xtaloscgm =0011 4 ax5051_xtaloscgm =0100 5 ax5051_xtaloscgm =0101 6 ax5051_xtaloscgm =0110 6.5 ax5051_xtaloscgm =0111 7 ax5051_xtaloscgm =1000 7.5 ax5051_xtaloscgm =1001 8 ax5051_ xtaloscgm =1010 8.5 ax5051_xtaloscgm =1011 9 ax5051_xtaloscgm =1100 9.5 ax5051_xtaloscgm =1101 10 ax5051_xtaloscgm =1110 10.5 ax5051_xtaloscgm =1111 11 c osc programmable tuning capacitors at pins clk16n and clk16p ax5051_x talcap=000000 default 2 pf ax5051_xtalcap=111111 33 pf c osc - lsb programmable tuning capacitors, increment per lsb of ax5051_xtalcap 0.5 pf f ext external clock input (tcxo) note 2, 3 15.5 16 25 mhz rin osc input dc impedance 10 k ? notes 1. tolerances and start - up times depend on the crystal used. depending on the rf frequency and channel spacing the ic must be calibrated to the exact crystal frequency using the readings of the register ax5051_trkfreq 2. if an external clock is used, it should be input via an ac coupling at pin clk16p with the oscillator powered up and ax5051_xtalcap=000000 3. lower frequencies than 15.5 mhz or higher frequencies than 25 mhz can be used. however not all typical rf frequencies can tha n be generated.
specifications www.onsemi.com AX8052F151 17 rf fre quency generation subsystem (synthesizer) symbol description condition min typ max unit f ref reference frequency note 1 16 24 mhz f range_hi frequency range bandsel=0 800 940 mhz f range_low bandsel=1 400 470 f reso frequency resolution 1 hz bw 1 synthesizer loop bandwidth vco current: vcoi=001 loop filter configuration: flt=01 charge pump current: pllcpi=010 100 khz bw 2 loop filter configuration: flt=01 charge pump current: pllcpi=001 50 bw 3 loop filter configuration: flt=11 charge pump current: pllcpi=010 200 bw 4 loop filter configuration: flt=10 charge pump current: pllcpi=010 500 t set1 synthesizer settling time for 1mhz step as typically required for rx/tx switching vco current: vco_i=001 loop filter configuration: fl t=01 charge pump current: pllcpi=010 15 s t set2 loop filter configuration: flt=01 charge pump current: pllcpi=001 30 t set3 loop filter configuration: flt=11 charge pump current: pllcpi=010 7 t set4 loop filter configuration: flt=10 charge pump current: pllcpi=010 3 t start1 synthesizer start - up time if crystal oscillator and reference are running vco current: vco_i=001 loop filter configuration: flt=01 charge pump current: pllcpi=010 25 s t start2 loop filter configuration: flt =01 charge pump current: pllcpi=001 50 t start3 loop filter configuration: flt=11 charge pump current: pllcpi=010 12
specifications www.onsemi.com AX8052F151 18 t start4 loop filter configuration: flt=10 charge pump current: pllcpi=010 5 pn868 1 synthesizer phase noise loop filter conf iguration: flt=01 charge pump current: pllcpi=010 vco current: vco_i=001 868 mhz, 50 khz from carrier - 85 dbc/hz 868 mhz, 100 khz from carrier - 90 868 mhz, 300 khz from carrier - 100 868 mhz, 2 mhz from carrier - 110 pn433 1 433 mhz, 5 0 khz from carrier - 90 433 mhz, 100 khz from carrier - 95 433 mhz, 300 khz from carrier - 105 433 mhz, 2 mhz from carrier - 115 pn868 2 synthesizer phase noise loop filter configuration: flt=01 charge pump current: pllcpi=001 vco curren t: vco_i=001 868 mhz, 50 khz from carrier - 80 dbc/hz 868 mhz, 100 khz from carrier - 90 868 mhz, 300 khz from carrier - 105 868 mhz, 2 mhz from carrier - 115 pn433 2 433 mhz, 50 khz from carrier - 90 433 mhz, 100 khz from carrier - 9 5 433 mhz, 300 khz from carrier - 110 433 mhz, 2 mhz from carrier - 122 notes: 1. ask, psk and 1 - 200 kbps fsk with 16 mhz crystal, 200 - 350 kbps fsk with 24 mhz crystal
specifications www.onsemi.com AX8052F151 19 transmitter symbol description condition min typ max unit sbr sig nal bit rate ask 1 600 kbps psk 10 600 fsk, note 2 1 350 802.15.4 (dsss) ask and psk 1 40 802.15.4 (dsss) fsk 1 16 ptx 868 transmitter power @868 mhz txrng=1111 locurst=1 15 dbm ptx 433 transmitter power @433 mhz txrng=1111 locurst=1 16 dbm ptx 868 - harm2 emission @ 2 nd harmonic note 1 - 50 dbc ptx 868 - harm3 emission @ 3 rd harmonic - 55 notes 1. additional low - pass filtering was applied to the antenna interface, see applications section. 2. 1 - 200 kbps with a 16 mhz crystal, 200 - 350 kbps with a 24 mhz crystal receiver datarate input sensitivity in dbm typ. at sma connector for ber=10 - 3 (433 mhz or 868 mhz) kbps ask fsk h=1 fsk h=4 fsk h=8 fsk h=16 psk 1.2 - 115 - 116 2 - 115 - 115 10 - 103 - 109 - 110 100 - 97 - 103 - 98 - 10 4 200 - 94 - 100 - 100 600 - 90 - 98
specifications www.onsemi.com AX8052F151 20 symbol description condition min typ max unit sbr signal bit rate ask 1 600 kbps psk 10 600 fsk 1 350 802.15.4 (dsss) ask and psk 1 40 802.15.4 (dsss) fsk 1 16 il maximum input level - 20 dbm cp 1db input referred compression point 2 tones separated by 100 khz - 35 dbm iip3 input referred ip3 - 25 rssir rssi control range 85 db rssis 1 rssi step size before digital channel filter; calculated from register ax5051_agccounter 0.625 db rssis 2 rssi step size after digital channel filter; calculated from registers ax5051_agccounter, ax5051_trkampl 0.1 db sel 868 adjacent channel suppression fsk 50 kbps, notes 1 & 2 18 db alternate channel suppression 19 adjacent ch annel suppression fsk 100 kbps, notes 1 & 3 16 db alternate channel suppression 30 adjacent channel suppression psk 200 kbps, notes 1 & 4 17 db alternate channel suppression 28 blk 868 blocking at +/ - 1mhz offset fsk 100 kbps, note 5 38 db blocking at - 2mhz offset 40 blocking at +/ - 10mhz offset 60 blocking at +/ - 100mhz offset 82 imrr 868 image rejection 30 notes 1. interferer/channel @ ber = 10 -3 , channel level is +10db above the typical sensitivity, the interfe ring signal is a random data signal (except psk200); both channel and interferer are modulated without shaping 2. fsk 50 kbps: 868 mhz, 200 khz channel spacing, 25 khz deviation, programming as recommended in ax5051 programming manual 3. fsk 100 kbps: 868 mhz, 400khz channel spacing, 50 khz deviation , programming as recommended in ax5051 programming manual 4. psk 200 kbps: 868 mhz, 400khz channel spacing, programming as recommended in ax5051 programming manual, interfering signal i s a constant wave 5. channel/block er @ ber = 10 -3 , channel level is +10db above the typical sensitivity, the blocker signal is a constant wave; channel signal is modulated without shaping, the image frequency lies 2 mhz above the wanted signal
specifications www.onsemi.com AX8052F151 21 low frequency crystal oscillator symbol desc ription condition min typ max unit f lpxtal crystal frequency 32 150 khz gm lpxosc transconductance oscillator lpxoscgm=00110 3.5 s lpxoscgm=01000 4.6 lpxoscgm=01100 6.9 lpxoscgm=10000 9.1 rin lpxosc input dc impedance 10 m ? int ernal low power oscillator symbol description condition min typ max unit f lposc oscillation frequency lposcfast=0 factory calibration applied. over the full voltage and temperature range 630 640 650 hz lposcfast=1 factory calibration applied. over the full voltage and temperature range 10.08 10.24 10.39 khz internal rc oscillator symbol description condition min typ max unit f frcosc oscillation frequency factory calibration applied. over the full temperature and voltage range 19.8 20 20.2 mhz
specifications www.onsemi.com AX8052F151 22 micr ocontroller symbol description condition min typ max unit t sysclkl sysclk low 27 ns t sysclkh sysclk high 21 ns t sysclkp sysclk period 47 ns t flwr flash write time 2 bytes 20 s t flpe flash page erase 1 kbytes 2 ms t fle flash secure eras e 64 kbytes 10 ms t flend flash endurance: erase cycles 10?000 100?000 cycles t flretroom flash data retention 25 o c see figure 3 for the lower limit set by the memory qualification 100 years t flrethot 85 o c see figure 3 for the lower limit set by the memory qualification 10 10 100 1000 10000 100000 15 25 35 45 55 65 75 85 temperature [ o c] data retention time [years] figure 3 flash memory qualification limit for data retention after 10k erase cycles
specifications www.onsemi.com AX8052F151 23 adc / comparator / temperature sen sor symbol description condition min typ max unit adcsr adc sampling rate gpadc mode 30 500 khz adcsr_t adc sampling rate temperature sensor mode 10 15.6 30 khz adcres adc resolution 10 bits v adcref adc reference voltage & comparator internal ref erence voltage 0.95 1 1.05 v z adc00 input capacitance 2.5 pf dnl differential nonlinearity +/ - 1 lsb inl integral nonlinearity +/ - 1 lsb off offset 3 lsb gain_err gain error 0.8 % adc in differential mode v abs_diff absolute voltages & common mode voltage in differential mode at each input 0 vdd_io v v fs_diff01 full swing input for differential signals gain x1 - 500 500 mv v fs_diff10 gain x10 - 50 50 mv adc in single ended mode v mid_se mid code input voltage in single ended mode 0.5 v v in_se00 input voltage in single ended mode 0 vdd_io v v fs_se01 full swing input for single ended signals gain x1 0 1 v comparators v comp_abs comparator absolute input voltage 0 vdd_io v v comp_com comparator input common mode 0 vdd_io - 0.8 v v compoff comparator input offset voltage 20 mv temperature sensor t rng temperature range - 40 85 c t res temperature resolution 0.1607 c/lsb t err_cal temperature error factory calibration applied - 2 +2 c
circuit description www.onsemi.com AX8052F151 24 5. circuit description the AX8052F151 is a single chip ultra - low - power rf - microcontroller soc primarily for use in srd bands. the on - chip transceiver consists of a fully integrated rf front - end with modulator, and demodulator. base band data process ing is implemented in an advanced and flexible communication controller that enables user friendly communication. the AX8052F151 contains a high speed microcontroller compatible to the industry standard 8052 instructi on set. it contains 64 kbytes of flash and 8.25 kbytes of internal sram. the AX8052F151 features 3 16 - bit general purpose timers with ? capability, 2 output compare units for generating pwm signals, 2 input compare units to record timings of external signals, 2 16- bit wakeup timers, a watchdog timer, 2 uarts, a master/slave spi controller, a 10 - bit 500 ksample/s a/d converter, 2 analog comparators, a temperature sensor, a 2 channel dma controller, and a dedicated aes crypto controller. debugging is aided by a dedicated hardware debug interface controller that connects using a 3 - wire protocol (1 dedicated wire, 2 shared with gpio) to the pc hosting the debug software. while the radio carrier/lo synthesizer can only be clocked by the crystal oscillator (carrier stability requirements dictate a high stability reference clock in the mhz range), the microcontroller and its peripherals provide extremely flexible clocking options. the system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from one of the following clock sources: the crystal oscillator, an internal high speed 20 mhz oscillator, an internal low speed 640 hz/10 khz oscillator, or the low frequency crystal oscillator. prescalers offer additional flexibility with their programmable divide by a power of two capability. to improve the accuracy of the internal oscillators, both oscillators may be slave d to the crystal oscillator. AX8052F151 can be operated from a 2.2 v to 3.6 v power supply over a temperature range of ? 40 o c to 85 o c, it consumes 11 - 45 ma for transmitting, depending on the output power, 19 ? 20 ma for receiving in high sensitivity mode and 17 ? 18 ma for receiving in low power mode. the AX8052F151 features make it an ideal interface for integration into various battery powered srd solutions such as ticketing o r as transceiver for telemetric applications e.g. in sensors. as primary application, the transceiver is intended for uhf radio equipment in accordance with the european telecommunication standard institute (etsi) specification en 300 220- 1 and the us fede ral communications commission (fcc) standard cfr47, part 15. the use of AX8052F151 in accordance to fcc par 15.247, allows for improved range in the 915 mhz band. additionally ax8 052f151 is compatible with the low frequency standards of 802.15.4 (zigbee) and suited for systems targeting compliance with wireless m - bus standard en 13757 - 4:2005 the AX8052F151 sends and receives data in frames. t his standard operation mode is called frame mode. pre and post ambles as well as checksums can be generated automatically. AX8052F151 supports any data rate from 1 kbps to 350 kbps for fsk and msk, from 1 kbps to 600 kbps for ask and from 10 kbps to 600 kbps for psk. to achieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX8052F151 are necessary, they are outlined in the following, for details see the ax5051 programming manual. spreading and despreading is possible on all data rates and modulation schemes. the net transfer rate is reduced by a factor of 15 in this case. for zigbee either 600 or 300 kbps modes have to be chosen. the receiver supports multi - channel operation for all data rates and modulation schemes.
circuit description www.onsemi.com AX8052F151 25 5.1. microcontroller the AX8052F151 microcontroller core executes the industry standard 8052 instruction set. unlike th e original 8052, many instructions are executed in a single cycle. the system clock and thus the instruction rate can be programmed freely from dc to 20mhz. memory architecture arbiter xram 0000-0fff arbiter xram 1000-1fff arbiter x registers 4000-7fff arbiter sfr registers 80-ff arbiter iram 00-ff arbiter flash 0000-ffff aes dma x bus ax8052 sfr bus iram bus code bus cache prefetch figure 4 ax8052 memory a rchitecture the ax8052 microcontroller features the highest bandwidth memory architecture of its class. figure 4 shows the memory architecture. three bus masters may initiate bus cycles: ? the ax8052 microcontroller core ? the direct memory access (dma) engine ? the advanced encryption standard (aes) engine bus targets include: ? two individual 4 kbytes ram blocks located in x address space, which can be simultaneously accessed and individually shut down or retained during sleep mode ? a 256 byte ram located in internal address space, which is always retained during sleep mode ? a 64 kbytes flash memory located in code space. ? special function registers (sfr) located in internal address space accessible using direct address mode instructions ? add itional registers located in x address space (x registers)
circuit description www.onsemi.com AX8052F151 26 the upper half of the flash memory may also be accessed through the x address space. this simplifies and makes the software more efficient by reducing the need for generic pointers 2 . sfr registers are also accessible through x address space, enabling indirect access to sfr registers. this allows driver code for multiple identical peripherals (such as uarts or timers) to be shared. the 4 word 16 bit fully associative cache and a pre - fetch controlle r hide the latency of the flash. the ax8052 memory architecture is fully parallel. all bus masters may simultaneously access different bus targets during each system clock cycle. each bus target includes an arbiter that resolves access conflicts. each arbi ter ensures that no bus master can be starved. both 4 kbytes ram blocks may be individually retained or switched off during sleep mode. the 256 byte ram is always retained during sleep mode. the aes engine accesses memory 16bits at a time. it is therefore slightly faster to align its buffers on even addresses. memory map xram flash 0000-007f 0080-00ff 0100-1fff 2000-207f 2080-3f7f 3f80-3fff 4000-4fff 5000-5fff 6000-7fff 8000-fbff fc00-ffff address calibration data iram iram p (code) space x space i (internal) space direct access indirect access sfr iram sfr rreg rreg (nb) xreg flash calibration data figure 5 ax8052 memory map the ax8052, like the other industry standard 8052 compatible microcontrollers, uses a harvard architecture. multiple address spaces are used to access code and data. figure 5 shows the ax8052 memory map. 2 generic pointers include, in addition to the address, an address space tag.
circuit description www.onsemi.com AX8052F151 27 the ax8052 uses p or code space to access its program. code space may also be read using the movc instruction. smaller amounts of data can be placed in the internal 3 or data space. a distinction is made in the upper half of the data space between direct accesses ( mov reg,addr ; mov addr,reg ) and indirect accesses ( mov reg,@ri ; mov @ri,reg ; push ; pop ); direct accesses are routed to the spe cial function registers, while indirect accesses are routed to the internal ram. large amounts of data can be placed in the external or x space. it can be accessed using the movx instructions. special function registers, as well as additional microcontroll er registers (xreg) and the radio registers (rreg) are also mapped into the x space. detailed documentation of the special function registers (sfr) and additional microcontroller registers can be found in the ax8052 programming manual. the radio registers are documented in the ax5051 programming manual. register addresses given in the ax5051 programming manual are relative to the beginning of rreg, i.e. 0x4000 must be added to these addresses. it is recommended that the axsem provided AX8052F151.h header fi le is used; radio registers are prefixed with ax5051_ in the AX8052F151.h header file to avoid clashes of same - name radio registers with ax8052 registers. normally, accessing radio registers through the rreg address range is adequate. since radio register accesses have a higher latency than other ax8052 registers, the ax8052 provides a method for non - blocking access to the radio registers. accessing the rreg (nb) address range initiates a radio register access, but does not wait for its completion. the deta ils of mechanism is documented in the radio interface section of the ax8052 programming manual. the flash memory is organized as 64 pages of 1 kbytes each. each page can be individually erased. the write word size is 16 bits. the last 1 kbyte page is dedic ated to factory calibration data and should not be overwritten. power management the microcontroller power mode can be selected independently from the transceiver. the microcontroller supports the following power modes: pcon register name description 00 r unning the microcontroller and all peripherals are running. current consumption depends on the system clock frequency and the enabled peripherals and their clock frequency. 01 standby the microcontroller is stopped. all register and memory contents are re tained. all peripherals continue to function normally. current consumption is determined by the enabled peripherals. standby is exited when any of the enabled interrupts become active. 10 sleep the microcontroller and its peripherals, except gpio and the system controller, are shut down. their register settings are lost. the internal ram is retained. the external ram is split into two 4kbyte blocks. software can determine individually for both blocks whether contents of that block are to be retained or los t. sleep can be exited 3 the origin of internal versus external (x) space is historical. external space used to be outside of the chip on the original 805 2 microcontrollers.
circuit descr iption www.onsemi.com AX8052F151 28 by any of the enabled gpio or system controller interrupts. for most applications this will be a gpio or wakeup timer interrupt. 11 deepsleep the microcontroller, all peripherals and the transceiver are shut down. only 4 bytes of sc ratch ram are retained. deepsleep can only be exited by tying the pb3 pin low. clocking lposc calib frcosc calib wakeup timer wdt clock monitor prescaler 1,2,4,... frcosc xosc lpxosc lposc interrupt internal reset sysclk glitch free clock switch system clock figure 6 clock system diagram the system clock can be derived from any of the following clock sources: ? the crys tal oscillator (rf reference oscillator, typically 16 mhz, via sysclk) ? the low speed crystal oscillator (typical 32 khz tuning fork) ? the internal high speed rc (20 mhz) oscillator ? the internal low power (640 hz/10 khz) oscillator an additional pre - scaler a llows the selected oscillator to be divided by a power of two. after reset, the microcontroller starts with the internal high speed rc oscillator selected and divided by two. i.e. at start - up, the microcontroller runs with 10 mhz 10%. clocks may be switc hed any time by writing to the clkcon register. in order to prevent clock glitches, the switching takes approximately 2(t 1 +t 2 ), where t 1 and t 2 are the periods of the old and the new clock. switching
circuit description www.onsemi.com AX8052F151 29 may take longer if the new oscillator first has to star t up. internal oscillators start up instantaneously, but crystal oscillators may take a considerable amount of time to start the oscillation. clkstat can be read to determine the clock switching status. a programmable clock monitor resets the clkcon regist er when no system clock transitions are found during a programmable time interval, thus reverts to the internal rc oscillator. both internal oscillators can be slaved to one of the crystal oscillators to increase the accuracy of the oscillation frequency. while the reference oscillator runs, the internal oscillator is slaved to the reference frequency by a digital frequency locked loop. when the reference oscillator is switched off, the internal oscillator continues to run unslaved with the last frequency s etting. reset and interrupts after reset, the microcontroller starts executing at address 0x0000. several events can lead to resetting the microcontroller core: ? por or hardware reset_n pin activated and released ? leaving sleep or deepsleep mode ? watchdog res et ? software reset the reset cause can be determined by reading the pcon register. the microcontroller supports 22 interrupt sources. each interrupt can be individually enabled and can be programmed to have one of two possible priorities. the interrupt vect ors are located at 0x0003, 0x000b, ?, 0x00ab. debugging a hardware debug unit considerably eases debugging compared to other 8052 microcontrollers. it allows to reliably stop the microcontroller at breakpoints even if the stack is smashed. the debug unit c ommunicates with the host pc running the debugger using a 3 wire interface. one wire is dedicated (dbg_en), while two wires are shared with gpio pins (pb6, pb7). when dbg_en is driven high, pb6 and pb7 convert to debug interface pins and the gpio functiona lity is no longer available. a pin emulation feature however allows bits pinb[7:6] to be set and portb[7:6] and dirb[7:6] to be read by the debugger software. this allows for example switches or leds connected to the pb6, pb7 pins to be emulated in the deb ugger software whenever the debugger is active. in order to protect the intellectual property of the firmware developer, the debug interface can be locked using a developer - selectable 64 - bit key. the debug interface is then disabled and can only be enabled with the knowledge of this 64 - bit key. therefore, unauthorized persons cannot read the firmware through the debug interface, but debugging is still possible for authorized persons. secure erase can be initiated without key knowledge; secure erase ensures that the main flash array is completely erased before erasing the key, reverting the chip into factory state. the debuglink peripheral looks like an uart to the microcontroller, and allows exchange of data between the microcontroller and the host pc withou t disrupting program execution.
circuit description www.onsemi.com AX8052F151 30 5.2. timer, output compare and input capture the AX8052F151 features three general purpose 16 - bit timers. each timer can be clocked by the system clock, any of the available oscillators, or a dedicated input pin. the timers also feature a programmable clock inversion, a programmable prescaler that can divide by powers of two, and an optional clock synchronization logic that synchronizes the clock to the system clock. all three counters are id entical and feature four different counting modes, as well as a ? mode that can be used to output an analog value on a dedicated digital pin only employing a simple rc lowpass filter. two output compare units work in conjunction with one of the timers to generate pwm signals. two input capture units work in conjunction with one of the timers to measure transitions on an input signal. for software timekeeping, two additional 16 - bit wakeup timers with 4 16 - bit event registers are provided, generating an inte rrupt on match events. 5.3. uart the AX8052F151 features two universal asynchronous receiver transmitters. they use one of the timers as baud rate generator. word length can be programmed from 5 to 9 bits. 5.4. spi master/slav e controller the AX8052F151 features a master/slave spi controller. both 3 and 4 wire spi variants are supported. in master mode, any of the on - chip oscillators or the system clock may be selected as clock source. an additional prescaler with divide by two capability provides additional clocking flexibility. shift direction, as well as clock phase and inversion, are programmable.
circuit description www.onsemi.com AX8052F151 31 5.5. adc, analog comparators and temperature sensor temperature sensor adc core clock trigger gain ref vref 1v vddio pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ppp nnn frcosc lposc xosc lpxosc sysclk system clock one shot free running timer 0 timer 1 timer 2 pc4 adc result acomp1ref acomp1st/pa7/pc1 acomp1in acomp1inv acomp0in acomp0ref acomp0inv acomp0st/pa4/pc3 system clock adcconv adcclksrc 0.1, 1, 10 single ended 0.5v prescaler 1,2,4,8,... figure 7 adc block diagram the AX8052F151 features a 10 - bit, 500 ksample/s analog to digital converter. the adc supports both single ended and differential measurements. it uses an internal reference of 1 v. 1, 10 and 0.1 gain modes are provided. the adc may digitize signals on pa0?pa7, as well as vdd_io and an internal temperature sensor. the user can define four channels which are then converted sequentially and stored in four separate result registers . each channel configuration consists of the multiplexer and the gain setting.
circuit description www.onsemi.com AX8052F151 32 the AX8052F151 contains an on - chip temperature sensor. built - in calibration logic allows the temperature sensor to be calibrated in c, f or any other user defined temperature scale. the AX8052F151 also features two analog comparators. each comparator can either compare two voltages on dedicated pa pins, or one voltage against the internal 1v reference . the comparator output can be routed to a dedicated digital output pin or can be read by software. the comparators are clocked with the system clock. 5.6. dma controller the AX8052F151 features a dual channel dma engine. each dma channel can either transfer data from xram to almost any peripheral on chip, or from almost any peripheral to xram. both channels may also be cross - linked for memory - memory transfers. the dma channels use buffer descriptors to find the buffers wh ere data is to be retrieved or placed, thus enabling very flexible buffering strategies. the dma channels access xram in a cycle steal fashion. they access xram whenever xram is not used by the microcontroller. their priority is lower than the microcontrol ler, thus interfering very little with the microcontroller. additional logic prevents starvation of the dma controller. 5.7. aes engine the AX8052F151 contains a dedicated engine for the government mandated advanced encry ption standard (aes). it features a dedicated dma engine and reads input data as well as key stream data from the xram, and writes output data into a programmable buffer in the xram. the round number is programmable; the chip therefore supports aes - 128, ae s - 192, and aes - 256, as well as higher security proprietary variants. keystream (key expansion) is performed in software, adding to the flexibility of the aes engine. ecb (electronic codebook), cfb (cipher feedback) and ofb (output feedback) modes are direc tly supported without software intervention. 5.8. crystal oscillator (rf reference oscillator) the on - chip crystal oscillator allows the use of an inexpensive quartz crystal as the rf generation subsystem?s timing reference. although a wider range of crystal f requencies can be handled by the crystal oscillator circuit, it is recommended to use 16 mhz as reference frequency for ask and psk modulations independent of the data rate. for fsk it is recommended to use a 16 mhz crystal for data rates below 200 kbps an d 24 mhz for data rates above 200 kbps. the oscillator circuit is enabled by programming the transceiver ax5051 _pwrmode register. at power - up it is not enabled. to adjust the circuit?s characteristics to the quartz crystal being used, without using additi onal external components, both the transconductance and the tuning capacitance of the crystal oscillator can be programmed. the transconductance is programmed via register bits xtaloscgm[3:0] in register ax5051 _xtalosc .
circuit description www.onsemi.com AX8052F151 33 the integrated programmable tuning capacitor bank makes it possible to connect the oscillator directly to pins clk16n and clk16p without the need for external capacitors. it is programmed using bits xtalcap[5:0] in register ax5051 _xtalcap . to synchronize the receiver frequency to a carri er signal, the oscillator frequency could be tuned using the capacitor bank however, the recommended method to implement frequency synchronization is to make use of the high resolution rf frequency generation sub - system together with the automatic frequenc y control, both are described further down. alternatively a single ended reference (tcxo, cxo) may be used. the cmos levels should be applied to clk16p via an ac coupling with the crystal oscillator enabled. 5.9. sysclk output the sysclk pin outputs the refer ence clock signal divided by a programmable integer. divisions from 1 to 2048 are possible. for divider ratios > 1 the duty cycle is 50%. bits sysclk[3:0] in the ax5051 _pincfg1 register set the divider ratio. the sysclk output can be disabled. outputting a frequency that is identical to the if frequency (default 1 mhz) on the sysclk pin is not recommended during receive operation, since it requires extensive decoupling on the pcb to avoid interference. 5.10. power - on - reset (por) and reset_n input AX8052F151 has an integrated power - on - reset block which is edge sensitive to vdd_io. for many common application cases no external reset circuitry is required. however, if vdd_io ramps cannot be guaranteed, an external reset circ uit is recommended. for detailed recommendations and requirements see the ax8052 application note: power on reset. after por or reset all registers are set to their default values. the reset_n pin contains a weak pull - up. however, it is strongly recommende d to connect the reset_n pin to vdd_io if not used, for additional robustness. the AX8052F151 can be reset by software as well. the microcontroller is reset by writing 1 to the swreset bit of the pcon register. the tr ansceiver can be reset by first writing 1 and then 0 to the rst bit in the ax5051 _pwrmode register.
circuit description www.onsemi.com AX8052F151 34 5.11. ports vddio portx.y dirx.y special function paltx.y pinx read clock pinx.y interrupt intchgx.y analogx.y 65 k ? figure 8 port pin schematic figure 8 shows the gpio logic. the dir r egister bit determines whether the port pin acts as an output (1) or an input (0). if configured as an output, the palt register bit determines whether the port pin is connected to a peripheral output (1), or used as a gpio pin (0). in the latter case, the port register bit determines the port pin drive value. if configured as an input, the port register bit determines whether a pull - up resistor is enabled (1) or disabled (0). inputs have schmitt - trigger characteristic. port a inputs may be disabled by sett ing the analoga register bit; this prevents additional current consumption if the voltage level of the port pin is mid - way between logic low and logic high, when the pin is used as an analog input. port a, b and c pins may interrupt the microcontroller if their level changes. the intchg register bit enables the interrupt. the pin register bit reflects the value of the port pin. reading the pin register also resets the interrupt if interrupt on change is enabled.
transceiver www.onsemi.com AX8052F151 35 6. transceiver the transceiver block is controll able through its registers, which are mapped into the x data space of the micro controller. the transceiver block features its own 4 word 10 bit fifo. the microcontroller can either be interrupted at a programmable fifo fill level, or one of the dma ch annels can be instructed to transfer between xram and the transceiver fifo. 6.1. rf frequency generation subsystem the rf frequency generation subsystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscill ator to get the desired rf frequency. the advanced architecture of the synthesizer enables frequency resolutions of 1 hz, as well as fast settling times of 5 ? 50 s depending on the settings (see section 4.3 : ac characteristics ). fast settling times mean fast start - up and fast rx/tx switching, enabling low - power system design. for receive operation the rf freq uency is fed to the mixer, for transmit operation to the power - amplifier. the frequency must be programmed to the desired carrier frequency. the rf frequency shift by the if frequency that is required for rx operation, is automatically set when the recei ver is activated and does not need to be programmed by the user. the default if frequency is 1 mhz. it can be programmed to other values. changing the if frequency and thus the centre frequency of the digital channel filter can be used to adapt the blockin g performance of the device to specific system requirements. the synthesizer loop bandwidth can be programmed. this serves three purposes: 1. start - up time optimization, start - up is faster for higher synthesizer loop bandwidths 2. tx spectrum optimization, phas e - noise at 300 khz to 1 mhz distance from the carrier improves with lower synthesizer loop bandwidths 3. adaptation of the bandwidth to the data - rate. for transmission of fsk and msk it is required that the synthesizer bandwidth must be in the order of the da ta - rate. vco an on - chip vco converts the control voltage generated by the charge pump and loop filter into an output frequency. this frequency is used for transmit as well as for receive operation. the frequency can be programmed in 1 hz steps in the ax50 51 _freq registers. for operation in the 433 mhz band, the bandsel bit in the ax5051 _pllloop register must be programmed. vco auto - ranging the AX8052F151 has an integrated auto - ranging function, which allows to set the correct vco range for specific frequency generation subsystem settings automatically. typically it has to be executed after power - up. the function is initiated by setting the rng_start bit in the ax5051 _pllranging register. the bit is readable and a 0 indicates the end of the ranging process. the rngerr bit indicates the correct execution of the auto - ranging.
transceiver www.onsemi.com AX8052F151 36 loop filter and charge pump the AX8052F151 internal loop filter configuration together with the charge pum p current sets the synthesizer loop band width. the loop - filter has three configurations that can be programmed via the register bits flt[1:0] in register ax5051 _pllloop , the charge pump current can be programmed using register bits pllcpi[1:0] also in re gister ax5051 _pllloop . synthesizer bandwidths are typically 50 - 500 khz depending on the ax5051 _pllloop settings, for details see the section 4.3 : ac characteristics . registers register bits purpose ax5051_pllloop flt[1:0] synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possible. pllcpi[2:0] synthesizer charge pump current, recommended usage is to decrease the bandwidth (and improve the phase - noise) for low data - rate transmissions. bandsel switches between 868 mhz/915 mhz and 433 mhz bands ax5051_freq programming of the carrier frequency ax5051_iffreqhi, ax5051_iffreqlo programming of the if fr equency ax5051_pllranging initiate vco auto - ranging and check results
transceiver www.onsemi.com AX8052F151 37 6.2. rf input and output stage (antp/antn) the AX8052F151 uses fully differential antenna pins. rx/tx switching is handled internally. an external r x/tx switch is not required. lna the lna amplifies the differential rf signal from the antenna and buffers it to drive the i/q mixer. an external matching network is used to adapt the antenna impedance to the ic impedance. a dc feed to the regulated supply voltage vreg must be provided at the antenna pins. for recommendations, see section see the applications section. i/q mixer the rf signal from the lna is mixed down to an if of typically 1 mhz. i - and q - if signals are buffered for the analog if filter. pa in tx mode the pa drives the signal generated by the frequency generation subsystem out to the differential antenna terminals. the output power of the pa is programmed via bits txrng[3:0] in the register ax5051 _txpwr . output power as well as harmonic con tent will depend on the external impedance seen by the pa, recommendations are given in the applications section. 6.3. analog if filter the mixer is followed by a complex band - pass if filter, which suppresses the down - mixed image while the wanted signal is ampl ified. the center frequency of the filter is 1 mhz, with a passband width of 1 mhz. the rf frequency generation subsystem must be programmed in such a way that for all possible modulation schemes the if frequency spectrum fits into the passband of the anal og filter. 6.4. digital if channel filter and demodulator the digital if channel filter and the demodulator extract the data bit - stream from the incoming if signal. they must be programmed to match the modulation scheme as well as the data - rate. inaccurate prog ramming will lead to loss of sensitivity. the channel filter offers bandwidths of 40 khz up to 600 khz. for detailed instructions how to program the digital channel filter and the demodulator see the ax5051 programming manual, an overview of the register s involved is given in the following table. the register setups typically must be done once at power - up of the device.
transceiver www.onsemi.com AX8052F151 38 registers register remarks ax5051_cicdec this register programs the bandwidth of the digital channel filter. ax5051_dataratehi, ax5051_ dataratelo these registers specify the receiver bit rate, relative to the channel filter bandwidth. ax5051_tmggainhi, ax5051_tmggainlo these registers specify the aggressiveness of the receiver bit timing recovery. more aggressive settings allow the recei ver to synchronize with shorter preambles, at the expense of more timing jitter and thus a higher bit error rate at a given signal - to - noise ratio. ax5051_modulation this register selects the modulation to be used by the transmitter and the receiver, i.e. whether ask, psk , fsk, msk or oqpsk should be used. ax5051_phasegain, ax5051_freqgain, ax5051_freqgain2, ax5051_amplgain these registers control the bandwidth of the phase, frequency offset and amplitude tracking loops. recommended settings are provided in the ax5051 programming manual. ax5051_agcattack, ax5051_agcdecay these registers control the agc (automatic gain control) loop slopes, and thus the speed of gain adjustments. the faster the bit - rate, the faster the agc loop should be. recommended sett ings are provided in the ax5051 programming manual. ax5051_txrate these registers control the bit rate of the transmitter. ax5051_fskdev these registers control the frequency deviation of the transmitter in fsk mode. the receiver does not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass. 6.5. encoder the encoder is located between the framing unit, the demodulator and the modulator. it can optionally transform the bit - stream in the following ways: ? it can invert the bit stream. ? it can perform differential encoding. this means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level. differential encoding is useful for p sk, because psk transmissions can be received either as transmitted or inverted, due to the uncertainty of the initial phase. differential encoding / decoding removes this uncertainty. ? it can perform manchester encoding. manchester encoding ensures that th e modulation has no dc content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate. ? it can perform spectral shaping. spectral shaping removes dc content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitted data is cyclic. it does so without adding additional bits, i.e. wi thout changing the data rate. spectral shaping uses a self synchronizing feedback shift register.
transceiver www.onsemi.com AX8052F151 39 the encoder is programmed using the register ax5051 _encoding , details and recommendations on usage are given in the ax5051 programming manual. 6.6. framing and fifo most radio systems today group data into packets. the framing unit is responsible for converting these packets into a bit - stream suitable for the modulator, and to extract packets from the continuous bit - stream arriving from the demodulator. the frami ng unit supports four different modes: ? hdlc ? raw ? raw with preamble match ? 802.15.4 compliant the microcontroller communicates with the framing unit through a 4 level 10 bit fifo. the fifo decouples microcontroller timing from the radio (modulator and demod ulator) timing. the bottom 8 bits of the fifo contain transmit or receive data. the top 2 bit are used to convey meta information in hdlc and 802.15.4 modes. they are unused in raw and raw with preamble match modes. the meta information consists of packet begin / end information and the result of crc checks. the framing unit contains one fifo. its direction is switched depending on whether transmit or receive mode is selected. the fifo can be operated in polled or interrupt driven modes. in polled mode, the microcontroller must periodically read the fifo status register or the fifo count register to determine whether the fifo needs servicing. in interrupt mode empty, not empty, full, not full and programmable level interrupts are provided. interrupts are ack nowledged by removing the cause for the interrupt, i.e. by emptying or filling the fifo. to lower the interrupt load on the microcontroller, one of the dma channels may be instructed to transfer data between the transceiver fifo and the xram memory. this w ay, much larger buffers can be realized in xram, and interrupts need only be serviced if the larger xram buffers fill or empty.
transceiver www.onsemi.com AX8052F151 40 hdlc mode note: hdlc mode follows high - level data link control (hdlc, iso 13239) protocol. hdlc mode is the main framing mode of the AX8052F151 . in this mode, the AX8052F151 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (crc ) field. the packet structure is given in the following table. flag address control information fcs flag 8 bit 8 bit 8 or 16 bit variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit hdlc packets are delimited with flag sequences of content 0x7e. in AX8052F151 the meaning of address and control is user defined. the frame check sequence (fcs) can be programmed to be crc - ccitt, crc - 16 or crc - 32. the receiver checks the crc, the result can be retrieved fro m the fifo, the crc is appended to the received data. for details on implementing a hdlc communication see the ax5051 programming manual. raw mode in raw mode, the AX8052F151 does not perform any packet delimiting or byte synchronization. it simply serializes transmit bytes and de - serializes the received bit - stream and groups it into bytes. this mode is ideal for implementing legacy protocols in software. raw mode with preamble match raw mode with preamble match is sim ilar to raw mode. in this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern (called the preamble) in the receive bit - stream. when it detects the preamble, it aligns the de - serialization to it. the preamb le can be between 4 and 32 bits long. 802.15.4 (zigbee) dsss 802.15.4 uses binary phase shift keying (psk) with 300 kbit/s (868 mhz band) or 600 kbit/s (915 mhz band) on the radio. the usable bit rate is only a 15 th of the radio bit rate, however. a sprea ding function in the transmitter expands the user bit rate by a factor of 15, to make the transmission more robust. the despreader function of the receiver undoes that. in 802.15.4 mode, the AX8052F151 framing unit pe rforms the spreading and despreading function according to the 802.15.4 specification. in receive mode, the framing unit will also automatically search for the 802.15.4 preamble, meaning that no interrupts will have to be serviced by the microcontroller un til a packet start is detected.
transceiver www.onsemi.com AX8052F151 41 the 802.15.4 is a universal dsss mode, which can be used with any modulation or datarate as long as it does not violate the maximum data rate of the modulation being used. therefore the maximum dsss data rate is 16 kbps for fsk and 40 kbps for ask and psk. 6.7. rx agc and rssi AX8052F151 features two receiver signal strength indicators (rssi): 1. rssi before the digital if channel filter. the gain of the receiver is adjusted in order to keep the analog if filter output level inside the working range of the adc and demodulator. the register ax5051 _agccounter contains the current value of the agc and can be used as an rssi. the step size of this rssi is 0.625 db. the value can be used as soon as t he rf frequency generation sub - system has been programmed. 2. rssi behind the digital if channel filter. the demodulator also provides amplitude information in the ax5051 _trk_amplitude register. by combining both the ax5051 _agccounter and the ax5051 _trk_am plitude registers, a high resolution (better than 0.1db) rssi value can be computed at the expense of a few arithmetic operations on the microcontroller. formulas for this computation can be found in the ax5051 programming manual. 6.8. modulator depending on th e transmitter settings the modulator generates various inputs for the pa: modulation bit = 0 bit = 1 main lobe bandwidth max. bitrate ask pa off pa on bw=bitrate 600kbit/s fsk / msk ? f= - f deviation ? f=+f deviation bw=(1+h) ? bitrate 350kbit/s psk ? =0 0 ? =180 0 bw=bitrate 600kbit/s h = modulation index. it is the ratio of the deviation compared to the bit - rate; f deviation = 0.5 ? h ? bitrate, AX8052F151 can demodulate signals with h < 32. ask = amplitude shift keying fsk = frequency shift keying msk = minimum shift keying; msk is a special case of fsk, where h = 0.5, and therefore f deviation = 0.25 ? bitrate; the advantage of msk over fsk is that it can be demodulated more robustly. psk = phase shift keying oqpsk = offset quadrature shift keying. the AX8052F151 supports oqpsk. however, unless compatibility to an existing system is required, msk should be preferred. al l modulation schemes are binary.
transceiver www.onsemi.com AX8052F151 42 6.9. automatic frequency control (afc) the AX8052F151 has a frequency tracking register ax5051 _trkfreq to synchronize the receiver frequency to a carrier signal. for afc adjustment, the f requency offset can be computed with the following formula: fskmul bitrate trkfreq f = ? . fskmul is the fsk oversampling factor, it depends on the fsk bit rate and deviation used. to determine it for a specific case, see the ax5051 programming manual. for modu lations other than fsk, fskmul=1. 6.10. pwrmode register the AX8052F151 transceiver features its own independent power management, independent from the microcontroller. while the microcontroller power mode is controlled t hrough the pcon register, the ax5051 _pwrmode register controls which parts of the transceiver are operating. ax5051_pwrmode register name description 0000 powerdown all digital and analog transceiver functions, except the register file, are disabled. vr eg is reduced to conserve leakage power. the registers are still accessible. 0100 vregon all digital and analog transceiver functions, except the register file, are disabled. vreg, however is at its nominal value for operation, and all registers are acces sible. 0101 standby the crystal oscillator is powered on; receiver and transmitter are off. 1000 synthrx the synthesizer is running on the receive frequency. transmitter and receiver are still off. this mode is used to let the synthesizer settle on the c orrect frequency for receive. 1001 fullrx synthesizer and receiver are running. 1100 synthtx the synthesizer is running on the transmit frequency. transmitter and receiver are still off. this mode is used to let the synthesizer settle on the correct freq uency for transmit. 1101 fulltx synthesizer and transmitter are running. do not switch into this mode before the synthesizer has completely settled on the transmit frequency (in synthtx mode), otherwise spurious spectral transmissions will occur.
transceiver www.onsemi.com AX8052F151 43 a typ ical ax5051 _pwrmode sequence for a transmit session: step pwrmode[3:0] remarks 1 powerdown 2 standby the settling time is dominated by the crystal used, typical value 3ms. 3 synthtx the synthesizer settling time is 5 ? 50 s depending on settings, see section ac characteristics 4 fulltx data transmission 5 synthtx this step must be programmed after fulltx mode, or the device will not enter powerdown or standby mode. 6 powerdown a typical ax5051 _pwrmode sequence for a receive session: step pwrmod e[3:0] remarks 1 powerdown 2 standby the settling time is dominated by the crystal used, typical value 3ms 3 synthrx the synthesizer settling time is 5 ? 50 s depending on settings, see section ac characteristics 4 fullrx data reception 5 powerdown
transceiver www.onsemi.com AX8052F151 44 6.11. voltage regulator the AX8052F151 transceiver uses its own dedicated on - chip volt age regulator to create a stable supply voltage for the transceiver circuitry at pin vreg from the primary supply vdd_io. all vdda pins of the device must be connected to vreg. the antenna pins antp and antn must be dc biased to vreg. the i/o level of the digital pins is vdd_io. the voltage regulator requires a 1f low esr capacitor at pin vreg. in power - down mode the voltage regulator typically outputs 1.7 v at vreg, if it is powered - up its output rises to typically 2.5 v. at device power - up the regulator is in power - down mode. the voltage regulator must be powered - up before receive or transmit operations can be initiated. this is handled automatically when programming the device modes via the ax5051 _pwrmode register. register vreg contains status bits that can be read to check if the regulated voltage is above 1.3 v or 2.3 v, sticky versions of the bits are provided that can be used to detect low power events (brown - out detection).
application information www.onsemi.com AX8052F151 45 7. application information connecting to debug adapter gnd gnd vdda gnd antp antn gnd clk16p clk16n vreg pa7 pa6 pa5 pa4 gnd reset_n dbg_en pb7 pb6 pb5 pb4 tst1 tst2 vdd_io sysclk pc3 pc2 pc4 vdda pb3 pa3 pa2 pa1 pa0 vdd_io pc1 pc0 pb0 pb2 pb1 AX8052F151 100pf 4.7uf dbg_en dbg_rt_n gnd dbg_clk dbg_data gnd dbg_vdd jumper jp1 1 2 3 4 5 6 7 8 16 mhz xtal 32 khz xtal debug adapter connector 1uf vdd_io vdd_io figure 9 typical application diagram with connection to the debug adapter short jumper jp1 - 1 if it is desired to supply the target board from the debug adapter (50ma max). connect the bottom exposed pad of the AX8052F151 to ground. if the debugger is not running, pb6 and pb7 are not driven by the debug adapter. if the debugger is running, the pb6 and pb7 values that the software reads may be set using the pin emulation feature of the debugger. pb3 is driven by the debugger only to bring the AX8052F151 out of deep sleep. it is high impedance otherwise. the 32 khz crystal is optional, the fast crystal at pins clk16n and clk16p is used as ref erence frequency for the rf rx/tx. crystal load capacitances should be chosen according to the crystal ?s datasheet. at pins clk16n and clk16p they the internal programmable capacitors may be used, at pins pa3 and pa4 capacitors must be connected externall y. it is mandatory to add 1f (low esr) between vreg and gnd. decoupling capacitors are not all drawn. it is recommended to add 100nf decoupling capacitor for
application information www.onsemi.com AX8052F151 46 every vdda and vdd_io pin. in order to reduce noise on the antenna inputs it is recommended to ad d 27 pf on the vdd pins close to the antenna interface. the AX8052F151 has an integrated voltage regulator for the analog supply voltages, which generates a stable supply voltage vreg from the voltage applied at vdd_i o. use vreg to supply all the vdda supply pins and also to dc power to the pins antp and antn. 7.1. antenna interface circuitry the antp and antn pins provide rf input to the lna when AX8052F151 is in receiving mode, and rf output from the pa when AX8052F151 is in transmitting mode. a small antenna can be connected with an optional translation network. the network must provide dc power to the pa and lna. a biasing to vreg is necessar y. beside biasing and impedance matching, the proposed networks also provide low pass filtering to limit spurious emission. single - ended antenna interface optiona l filter stage to suppress tx harmonics cc1 cb1 lt2 50 ? single - ended equipment or antenna ic antenna pins vreg vreg lt1 lc2 lc1 cm1 lb1 cb2 lb2 cf1 cf2 lf1 ct1 ct2 cc2 cm2 figure 10 structure of the antenna interface to 5 0 ? single - ended equipment or antenna frequency band lc1,2 [nh] cc1,2 [pf] lt1,2 [nh] ct1,2 [pf] cm1,2 [pf] lb1,2 [nh] cb1,2 [pf] lf1 [nh] cf1,2 [pf] 868 / 915 mhz 68 0.9 12 18 2.4 12 2.7 0 ohm n.c. 433 mhz 120 2.2 39 7.5 6.0 27 5.2 0 ohm n.c
qfn40 package information www.onsemi.com AX8052F151 47 8. qfn40 pack age information 8.1. package outline qfn40 on AX8052F151 - v awl yyww notes 1. ?e? represents the basic terminal pitch 2. datum ?c? is the mounting surface with which the package is in contact. 3. ?3? specifies the vertical shift of the flat part of each terminal from the mounting surface. 4. dimension ?a? includes package warpage. 5. dimension ?b? applies to the metallised terminal and is measured between 0.15 to 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in the radius are 6. package dimension take reference from jedec mo - 220 7. awl yyww is the packaging lot code 8. v is the device version 9. rohs
qfn40 package information www.onsemi.com AX8052F151 48 8.2. qfn40 soldering profile profile feature pb - free process average ramp - up rate 3 c/sec max. preheat preheat temperature min t smin 150c temperature max t smax 200c time (t smin to t smax ) t s 60 ? 180 sec time 25c to peak temperature t 25 to peak 8 min max. reflow phase liquidus temperature t l 217c time over liquidus temperature t l 60 ? 150 sec peak temperature t p 260c time within 5c of actual peak temperature t p 20 ? 40 sec cooling phase ramp - down rate 6c/sec max. notes: all temperatures refer to the top side of the package, measured on the package body surface. time t p t l t smax t smin t 25 to peak t s t l 25c preheat reflow cooling t p temperature
qfn40 package information www.onsemi.com AX8052F151 49 8.3. qfn40 recommended pad layout 1. pcb land and solder masking recommendations are shown in figure 11. a = clearance from pcb thermal pad to solder mask opening, 0.0635 mm minimum b = clearance from edge of pcb thermal pad to pcb land, 0.2 mm minimum c = clearance from pcb land edge to solder mask opening to be as tight as possible to ensure that some s older mask remains between pcb pads d = pcb land length = qfn solder pad length + 0.1mm e = pcb land width = qfn solder pad width + 0.1 mm figure 11 pcb land and solder mask recommendations 2. thermal vias should be used on the pcb thermal pad (middle groun d pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. the number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 3. in creasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. in general, adding more metal through the pc board under the ic will improve operational heat trans fer, but will require careful attention to uniform heating of the board during assembly. 8.4. assembly process stencil design & solder paste application 1. stainless steel stencils are recommended for solder paste application. 2. a stencil thickness of 0.125 ? 0.150 mm (5 ? 6 mils) is recommended for screening. 3. for the pcb thermal pad, solder paste should be printed on the pcb by designing a stencil with an array of smaller openings that sum to 50% of the qfn exposed pad area. solder paste should be applied through an array of squares (or circles) as shown in figure 12. 4. the aperture opening for the signal pads should be between 50 - 80% of the qfn pad area as shown in figure 13. 5. optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 6. the fine pitch of the ic leads requires accurate alignment of the stencil and the printed circuit board. the stencil and printed circuit assembly should be aligned to within + 1 mi l prior to application of the solder paste. 7. no - clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water - soluble flux is used.
qfn40 package information www.onsemi.com AX8052F151 50 figure 12 solder paste application on exposed pad min imum 50% coverage 62% coverage maximum 80% coverage figure 13 : solder paste application on pins
device versions www.onsemi.com AX8052F151 51 9. device versions device marking ax8052 version ax5051 version AX8052F151 - 1 1 1 AX8052F151 - 2 1c 1 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsid iaries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trad e secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent - marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes n o warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liabi lity, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. s cillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or author ized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in wh ich the failure of the scillc product could create a situation where personal in jury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, bu yer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such u nintended or unauthorized use, even if such claim alleges that scillc was negligent regardi ng the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable copyright laws and is not for resale in any manner. p ublication ordering information literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 - 675- 2175 or 800 - 344 - 3860 toll free usa/canada fax: 303 - 675 - 2176 or 800 - 344 - 3867 toll free usa/canada email : orderlit@onsemi.com n. american t echnical support : 800 - 282 - 9855 toll free usa/canada. europe, m iddle east and africa technical support : phone: 421 33 790 2910 japan customer focus center phone: 81 - 3 - 5817 - 1050 on semiconductor website : www.onsemi .com order literature : http://www.onsemi.com/orderlit for additional i nformation, please contact your local sales representative

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